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| HSP45106/883 TM Data Sheet May 1999 FN2815.3 16-Bit Numerically Controlled Oscillator The Intersil HSP45106/883 is a high performance 16-bit quadrature Numerically Controlled Oscillator (NCO16). The NCO16 simplifies applications requiring frequency and phase agility such as frequency-hopped modems, PSK modems, spread spectrum communications, and precision signal generators. As shown in the Block Diagram, the HSP45106/883 is divided into a Phase/Frequency Control Section (PFCS) and a Sine/Cosine Section. The inputs to the Phase/Frequency Control Section consist of a microprocessor interface and individual control lines. The frequency resolution is 32 bits, which provides for resolution of better than 0.006Hz at 25.6MHz. User programmable center frequency and offset frequency registers give the user the capability to perform phase coherent switching between two sinusoids of different frequencies. Further, a programmable phase control register allows for phase control of better than 0.006o. In applications requiring up to 8 level PSK, three discrete inputs are provided to simplify implementation. The output of the PFCS is a 32-bit phase argument which is input to the Sine/Cosine Section for conversion into sinusoidal amplitude. The outputs of the Sine/Cosine Section are two 16-bit quadrature signals. The spurious free dynamic range of this complex vector is greater than 90dBc. For added flexibility when using the NCO16 in conjunction with DAC's, a choice of either parallel of serial outputs with either two's complement or offset binary encoding is provided. In addition, a synchronization signal is available which signals serial word boundaries. Features * This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * 25.6MHz Clock Rate * 32-Bit Center and Offset Frequency Control * 16-Bit Phase Control * 8 Level PSK Supported Through Three Pin Interface * Simultaneous 16-Bit Sine and Cosine Outputs * Output in Two's Complement or Offset Binary * <0.006Hz Tuning Resolution at 25.6MHz * Serial or Parallel Outputs * Spurious Frequency Components < -90dBc * 16-Bit Microprocessor Compatible Control Interface Applications * Direct Digital Synthesis * Quadrature Signal Generation * Modulation - FM, FSK, PSK (BPSK, QPSK, 8PSK) * Precision Signal Generation Ordering Information PART NUMBER HSP45106GM-25/883 TEMP. RANGE ( oC) -55 to 125 PACKAGE 85 Ld PGA PKG. NO. G85.A Block Diagram MICROPROCESSOR INTERFACE DISCRETE CONTROL SIGNALS CLOCK SIN/COS ARGUMENT PHASE/ FREQUENCY CONTROL SECTION 32 SINE/ COSINE SECTION SINE 16 COSINE 16 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved HSP45106/883 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output Voltage Applied . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PGA Package . . . . . . . . . . . . . . . . . . . . 36.0 7.0 Maximum Package Power Dissipation at 125oC PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.39W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Die Characteristics Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18,750 CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER Logical One Input Voltage Logical Zero Input Voltage Output HlGH Voltage SYMBOL VlH VIL VOH VOL II IO VIHC V ILC ICCSB ICCOP FT TEST CONDITIONS VCC = 5.5V VCC = 4.5V IOH = -400A VCC = 4.5V (Note 2) IOL = +2.0mA VCC = 4.5V (Note 2) VIN = VCC or GND VCC = 5.5V VOUT = VCC or GND VCC = 5.5V VCC = 5.5V VCC = 4.5V VIN = VCC or GND VCC = 5.5V, (Note 5) f = 25.6MHz VCC = 5.5V (Notes 3, 5) (Note 4) GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE ( oC) 55 TA +125 55 TA +125 55 TA +125 55 TA +125 55 TA +125 55 TA +125 55 TA +125 55 TA +125 55 TA +125 55 TA +125 55 TA +125 MIN 2.2 2.6 MAX 0.8 UNITS V V V Output LOW Voltage 1, 2, 3 - 0.4 V A A Input Leakage Current 1, 2, 3 -10 +10 Output Leakage Current 1, 2, 3 -10 +10 Clock lnput High Clock Input Low Standby Power Supply Current Operating Power Supply Current Functional Test NOTES: 1, 2, 3 1, 2, 3 1, 2, 3 3.0 - 0.8 500 V V A 1, 2, 3 - 205 mA 7, 8 - - - 2. Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 8mA/MHz. 4. Tested as follows: f = 1MHz, VIH = 2.6, VIL = 0.4, VOH 1.5V, VOL 1.5V, VIHC = 3.4V, and VILC = 0.4V. 5. Loading is as specified in the test load circuit with CL = 40pF. 2 HSP45106/883 TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS -25 (25.6MHz) PARAMETER CLK Period CLK High CLK Low WR Period WR High WR Low Setup Time A(2:0), CS to WR Going High Hold Time A(2:0), CS from WR Going High Setup Time C(15:0) to WR Going High Hold Time C(15:0) from WR Going High Setup Time WR High to CLK High Setup Time MOD(2:0) to CLK Going High Hold Time MOD(2:0) from CLK Going High Setup Time ENPOREG, ENOFREG, ENCFREG, ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC, BINFMT, TEST, PAR/SER, PACI, INITTAC to CLK Going High Setup Time ENPOREG, ENOFREG, ENCFREG, ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC, BINFMT, TEST, PAR/SER, PACI, INITTAC from CLK Going High CLK to Output Delay SIN(15:0), COS(15:0), TICO CLK to Output Delay DACSTRB Output Enable Time NOTES: 6. AC Testing: VCC = 4.5V and 5.5V. Inputs are driven at 3.0V for Logic "1" and 0.0V for a Logic "0". Input and output timing measurements are made at 1.5V for both a Logic "1" and 0". CLK is driven at 4.0V and 0V and measured at 2.0V. Output load per test load circuit with switch closed and CL = 40pF. 7. Transition is measured at 200mV from steady state voltage with loading as specified by test load circuit and CL = 40pF. 8. If ENOFRCTL, ENCFRACTL, ENTICTL, or ENPHREG are active, care must be taken to not violate setup and hold times to these registers when writing data into the chip via the C(15:0) port. SYMBOL t CP t CH tCL tWP tWH tWL tAWS tAWH tCWS tCWH tWC tMCS tMCH tECS Note 8 NOTES GROUP A SUBGROUP 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE ( oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 39 15 15 39 15 15 13 MAX UNITS ns ns ns ns ns ns ns 9, 10, 11 2 - ns 9, 10, 11 15 - ns 9, 10, 11 1 - ns 9, 10, 11 9, 10, 11 16 15 - ns ns 9, 10, 11 1 - ns 9, 10, 11 12 - ns tECH 9, 10, 11 -55 TA 125 1 - ns tDO tDSO tOE Note 7 9, 10, 11 -55 TA 125 -55 TA 125 -55 TA 125 - 18 ns 9, 10, 11 9, 10, 11 2 - 18 12 ns ns 3 HSP45106/883 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS -25 (25MHz) PARAMETER Input Capacitance SYMBOL CIN CONDITIONS VCC = Open, f = 1MHz, all measurements are referenced to device GND. VCC = Open, f = 1MHz, all measurements are referenced to device GND. NOTES 9 TEMPERATURE (oC) TA = 25 TA = 25 -55 TA 125 -55 TA 125 -55 TA 125 MIN - MAX 10 UNITS pF Output Capacitance COUT tOEZ tOR tOF 9 - 10 pF Output Disable Delay Output Rise Time Output Fall Time NOTES: 9, 10 From 0.8V to 2.0V From 20.V to 0.8V 9, 10 9, 10 - 15 8 8 ns ns ns 9. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 10. Loading is as specified in the test load circuit with switch closed and CL = 40pF. TABLE 4. ELECTRICAL TEST REQUIREMENTS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 4 HSP45106/883 Burn-In Circuit HSP45106/833 (PGA) 11 L K J H G F E D C B A GND FMT INIPAC ENP HAC ENTI REG ENCF REG CS VCC 10 SIN0 VCC PAR/ SEL PACI INITT AC ENPO REG GND TEST C10 A1 GND C15 C14 C12 C11 C9 C13 C8 C6 VCC C7 C4 C5 INHOF R ENOF REG WR COS6 COS7 9 SIN1 CLK 8 SIN3 SIN2 7 SIN5 VCC SIN6 6 SIN4 SIN8 SIN7 5 SIN9 SIN10 SIN11 4 SIN12 GND 3 SIN13 SIN15 2 SIN14 OES OEC COS2 COS4 COS8 1 DAC STRB COSO COS1 COS3 COS5 VCC L K J H G F E D C B A PIN "A1" COS11 COS10 COS9 GND COS12 MOD2 MOD0 MOD1 PMSEL A2 A0 INDEX PIN COS15 COS13 C1 C3 TICO C2 COS14 C0 PGA PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 NOTES: PIN NAME C0 C2 C3 C5 C7 C8 C11 C14 GND A0 PMSEL COS14 TICO C1 C4 VCC C13 C12 C15 A1 A2 BURN-IN SIGNAL F7 F7 F7 F8 F8 F10 F10 F11 GND F8 F14 VCC /2 VCC /2 F7 F8 VCC F11 F11 F11 F7 F10 PGA PIN B11 C1 C2 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 E11 F1 F2 F3 PIN NAME MOD1 COS13 COS15 C6 C9 C10 MOD0 MOD2 COS12 GND TEST VCC COS9 COS10 COS11 WR GND CS VCC COS8 COS7 BURN-IN SIGNAL F13 V CC /2 V CC /2 F8 F10 F10 F12 F14 V CC /2 GND F14 VCC V CC /2 V CC /2 V CC /2 F4 GND F6 VCC V CC /2 V CC /2 PGA PIN F9 F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11 J1 J2 J5 J6 J7 J10 J11 K1 PIN NAME ENOFREG ENPOREG ENCFREQ COS5 COS4 COS6 INHOFR INITTAC ENTIREG COS3 COS2 PACI ENPHAC COS1 OEC SIN11 SIN7 SIN6 PAR/SER INITPAC COS0 BURN-IN SIGNAL F8 F4 F7 VCC /2 VCC /2 VCC /2 F11 F13 F12 VCC /2 VCC /2 F11 F10 VCC /2 F14 VCC /2 VCC /2 VCC /2 F13 F12 VCC /2 PGA PIN K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 PIN NAME OES SIN15 GND SIN10 SIN8 VCC SIN2 CLK VCC BINFMT DACSTRB SIN14 SIN13 SIN12 SIN9 SIN4 SIN5 SIN3 SIN1 SIN0 GND BURN-IN SIGNAL F14 VCC /2 GND VCC /2 VCC /2 VCC VCC /2 F0 VCC F6 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 GND 11. V CC /2 (2.7V 10%) used for outputs only. 12. 47k (20%) resistor connected to all pins except VCC and GND. 13. V CC = 5.5V 0.5V. 14. 0.1F (min) capacitor between VCC and GND per position. 15. F0 = 100kHz 10%, F1 = F0/2, F2 = F1/2...., F11 = F10/2, 40% - 60% Duty Cycle. 16. Input voltage limits: VIL = 0.8V max., VIH = 4.5V 10%. 5 HSP45106/883 Die Characteristics DIE DIMENSIONS: 251 mils x 240 mils x 19 1mils METALLIZATION: Type: Si-Al, or Si-Al-Cu Thickness: 8kA GLASSIVATION: Type: Nitrox Thickness: 10kA WORST CASE CURRENT DENSITY: 0.8 x 105 A/cm 2 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite 100 Irvine, CA 92618 TEL: (949) 341-7000 FAX: (949) 341-7123 Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7946 EUROPE Intersil Europe Sarl Ave. William Graisse, 3 1006 Lausanne Switzerland TEL: +41 21 6140560 FAX: +41 21 6140579 ASIA Intersil Corporation Unit 1804 18/F Guangdong Water Building 83 Austin Road TST, Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433 6 |
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